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AMD Details Zen Architecture Near IDF, 40% IPC Increase

Posted on August 18, 2016

While Intel's Developer Forum is underway in San Francisco, not far from AMD in Sunnyvale, the x64 creators held a press conference to demonstrate Zen CPU performance. Based strictly on the presentation, AMD shows a 40% IPC (Instructions Per Clock) over Vishera. The demonstration used a 16T processor, the “Summit Ridge” chip that's been discussed a few times, which runs 8 cores with simultaneous multi-threading (SMT) for 16 total threads. For the non-gaming market, CPU codename “Naples” was also present, a 32C/64T Zen server processor in a dual-CPU Windows server.

AMD detailed more of the Zen architecture in an official capacity, commenting on new caching routines and branch prediction, accompanied by the SMT changes that shift AMD away from its modular Bulldozer architecture. AMD made mention of “fanless 2-in-1s” in addition to high-performance CPUs and embedded systems.

The Summit Ridge block diagram, above, increases issue width and execution resources by 1.5x over Excavator, with a 1.75x instruction scheduler window increase over Excavator. Single-thread performance improves by greater instruction-level parallelism, and AMD still drives a big focus on integer units, with Summit Ridge running 6 schedulers under its Integer Rename, each assigned to an ALU. This particular Zen block diagram shows 4 ALUs and 2 AGUs, the latter of which pipe into L/S (load/store) queues. Zen can perform 2 loads and 1 store with each cycle, and caches in a 32K 8-way D-Cache.


The FPU side of the chip runs 2 MULs and 2 ADDs for floating point operations, with a single scheduler flanked by the FP Rename and FP Register file. Cache has been mostly unified, with L3 Cache (at 8MB) now shared, and L2 Cache unified for instruction use. The 5x increase in cache per core contributes in a non-trivial fashion to AMD's IPC gains.

As with the new Polaris GPU architecture, Zen uses 14nm FinFET manufacturing process, improving power efficiency in-step with clock gating and advanced sleep states.

AMD claimed identical Blender rendering performance, clock-for-clock, to an Intel i7 8C/16T BW-E part.

Summit Ridge will launch first of the known Zen CPUs, and will sell alongside the AM4 socketed boards that are already in production. AM4 unifies AMD's APU and CPU platforms, merging both disparate sockets into a single socket type; this means that, as of today, there will be no continuation of the FM line. FM and AM CPUs will now be able to use one motherboard. From a maintenance perspective, this obviously allows for boards to be re-used for multiple deployments in different PC setups. Bristol Ridge will function in AM4, and System Integrators will be shipping AM4 socketed systems in 2H16.

AM4 moves AMD to modern, native support of updated storage interfaces and buses, including NVMe native support, SATA-e, USB3.1 Gen2 at 10Gb/s, DDR4 native support, and PCI-e 3.x support.

Additional Zen architecture updates will release next week.

- Steve "Lelldorianx" Burke.